Project IceStorm – iCE40 HX8K LOGIC Tile (32 32)

This page describes the LOGIC Tile (32 32), what nets and configuration bits it has and how it is connected to its neighbourhood.

IO Tile (30 33)	IO Tile (31 33)	IO Tile (32 33)
LOGIC Tile (30 32)	LOGIC Tile (31 32)	LOGIC Tile (32 32)	IO Tile (33 32)
LOGIC Tile (30 31)	LOGIC Tile (31 31)	LOGIC Tile (32 31)	IO Tile (33 31)
LOGIC Tile (30 30)	LOGIC Tile (31 30)	LOGIC Tile (32 30)	IO Tile (33 30)

Configuration Bitmap

A LOGIC Tile has 864 config bits in 16 groups of 54 bits each:
 B0[53:0],  B1[53:0],  B2[53:0],  B3[53:0],  B4[53:0],  B5[53:0],  B6[53:0],  B7[53:0],
 B8[53:0],  B9[53:0], B10[53:0], B11[53:0], B12[53:0], B13[53:0], B14[53:0], B15[53:0]

Nets and Connectivity

This section lists all nets in the tile and how this nets are connected with nets from cells in its neighbourhood.

List of nets in LOGIC Tile (32 32)

Global Networks

• glb2local_{0,1,2,3}
• glb_netwk_{0,1,2,3,4,5,6,7}

Local Tracks

• local_g0_{0,1,2,3,4,5,6,7}
• local_g1_{0,1,2,3,4,5,6,7}
• local_g2_{0,1,2,3,4,5,6,7}
• local_g3_{0,1,2,3,4,5,6,7}

Logic Block

• carry_in
• carry_in_mux
• lutff_{0,1,2,3,4,5,6,7}/cout
• lutff_{0,1,2,3,4,5,6,7}/in_0
• lutff_{0,1,2,3,4,5,6,7}/in_1
• lutff_{0,1,2,3,4,5,6,7}/in_2
• lutff_{0,1,2,3,4,5,6,7}/in_3
• lutff_{0,1,2,3,4,5,6}/lout
• lutff_{0,1,2,3,4,5,6,7}/out
• lutff_global/cen
• lutff_global/clk
• lutff_global/s_r

Neighbourhood

• neigh_op_bnl_{0,1,2,3,4,5,6,7}
• neigh_op_bnr_{0,1,2,3,4,5,6,7}
• neigh_op_bot_{0,1,2,3,4,5,6,7}
• neigh_op_lft_{0,1,2,3,4,5,6,7}
• neigh_op_rgt_{0,1,2,3,4,5,6,7}
• neigh_op_tnl_{0,1,2,3,4,5,6,7}
• neigh_op_tnr_{0,1,2,3,4,5,6,7}
• neigh_op_top_{0,1,2,3,4,5,6,7}

Span-4 Vertical

• sp4_v_b_{0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47}
• sp4_v_t_{36,37,38,39,40,41,42,43,44,45,46,47}

Span-4 Right Vertical

• sp4_r_v_b_{0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47}

Span-4 Horizontal

• sp4_h_l_{36,37,38,39,40,41,42,43,44,45,46,47}
• sp4_h_r_{0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47}

Span-12 Vertical

• sp12_v_b_{0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23}
• sp12_v_t_{22,23}

Span-12 Horizontal

• sp12_h_l_{22,23}
• sp12_h_r_{0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23}

Nets and their permanent connections to nets in neighbour tiles

Global Networks

Local Tracks

Logic Block

Logic Unit 0

Logic Unit 1

Logic Unit 2

Logic Unit 3

Logic Unit 4

Logic Unit 5

Logic Unit 6

Logic Unit 7

Neighbourhood

Span-4 Vertical

Span-4 Right Vertical

Span-4 Horizontal

Span-12 Vertical

Span-12 Horizontal

Routing Configuration

This section lists the routing configuration bits in the tile. All routing resources are directional tristate buffers that are in tristate mode in the all-zeros configuration.

Global Networks