hierarchy - check, expand and clean up design hierarchy

    hierarchy [-check] [-top <module>]
    hierarchy -generate <cell-types> <port-decls>

In parametric designs, a module might exists in several variations with
different parameter values. This pass looks at all modules in the current
design an re-runs the language frontends for the parametric modules as

        also check the design hierarchy. this generates an error when
        an unknown module is used as cell type.

        like -check, but also thow an error if blackbox modules are
        instantiated, and throw an error if the design has no top module

        by default the hierarchy command will not remove library (blackbox)
        modules. use this option to also remove unused blackbox modules.

    -libdir <directory>
        search for files named <module_name>.v in the specified directory
        for unknown modules and automatically run read_verilog for each
        unknown module.

        per default this pass also converts positional arguments in cells
        to arguments using port names. this option disables this behavior.

        per default this pass adjusts the port width on cells that are
        module instances when the width does not match the module port. this
        option disables this behavior.

        per default this pass sets the "keep" attribute on all modules
        that directly or indirectly contain one or more $assert cells. this
        option disables this behavior.

    -top <module>
        use the specified top module to built a design hierarchy. modules
        outside this tree (unused modules) are removed.

        when the -top option is used, the 'top' attribute will be set on the
        specified top module. otherwise a module with the 'top' attribute set
        will implicitly be used as top module, if such a module exists.

        automatically determine the top of the design hierarchy and mark it.

In -generate mode this pass generates blackbox modules for the given cell
types (wildcards supported). For this the design is searched for cells that
match the given types and then the given port declarations are used to
determine the direction of the ports. The syntax for a port declaration is:


Input ports are specified with the 'i' prefix, output ports with the 'o'
prefix and inout ports with the 'io' prefix. The optional <num> specifies
the position of the port in the parameter list (needed when instantiated
using positional arguments). When <num> is not specified, the <portname> can
also contain wildcard characters.

This pass ignores the current selection and always operates on all modules
in the current design.