synth_ice40 - synthesis for iCE40 FPGAs

    synth_ice40 [options]

This command runs synthesis for iCE40 FPGAs.

    -top <module>
        use the specified module as top module (default='top')

    -blif <file>
        write the design to the specified BLIF file. writing of an output file
        is omitted if this parameter is not specified.

    -edif <file>
        write the design to the specified edif file. writing of an output file
        is omitted if this parameter is not specified.

    -run <from_label>:<to_label>
        only run the commands between the labels (see below). an empty
        from label is synonymous to 'begin', and empty to label is
        synonymous to the end of the command list.

    -noflatten
        do not flatten design before synthesis

    -retime
        run 'abc' with -dff option

    -nocarry
        do not use SB_CARRY cells in output netlist

    -nobram
        do not use SB_RAM40_4K* cells in output netlist

    -abc2
        run two passes of 'abc' for slightly improved logic density


The following commands are executed by this synthesis command:

    begin:
        read_verilog -lib +/ice40/cells_sim.v
        hierarchy -check -top <top>

    flatten:    (unless -noflatten)
        proc
        flatten
        tribuf -logic
        deminout

    coarse:
        synth -run coarse

    bram:    (skip if -nobram)
        memory_bram -rules +/ice40/brams.txt
        techmap -map +/ice40/brams_map.v

    fine:
        opt -fast -mux_undef -undriven -fine
        memory_map
        opt -undriven -fine
        techmap -map +/techmap.v -map +/ice40/arith_map.v
        abc -dff    (only if -retime)
        ice40_opt

    map_ffs:
        dffsr2dff
        dff2dffe -direct-match $_DFF_*
        techmap -map +/ice40/cells_map.v
        opt_expr -mux_undef
        simplemap
        ice40_ffinit
        ice40_ffssr
        ice40_opt -full

    map_luts:
        abc          (only if -abc2)
        ice40_opt    (only if -abc2)
        techmap -map +/ice40/latches_map.v
        abc -lut 4
        clean

    map_cells:
        techmap -map +/ice40/cells_map.v
        clean

    check:
        hierarchy -check
        stat
        check -noinit

    blif:
        write_blif -gates -attr -param <file-name>

    edif:
        write_edif <file-name>