synth_xilinx - synthesis for Xilinx FPGAs

    synth_xilinx [options]

This command runs synthesis for Xilinx FPGAs. This command does not operate on
partly selected designs. At the moment this command creates netlists that are
compatible with 7-Series Xilinx devices.

    -top <module>
        use the specified module as top module

    -edif <file>
        write the design to the specified edif file. writing of an output file
        is omitted if this parameter is not specified.

    -run <from_label>:<to_label>
        only run the commands between the labels (see below). an empty
        from label is synonymous to 'begin', and empty to label is
        synonymous to the end of the command list.

    -flatten
        flatten design before synthesis

    -retime
        run 'abc' with -dff option


The following commands are executed by this synthesis command:

    begin:
        read_verilog -lib +/xilinx/cells_sim.v
        read_verilog -lib +/xilinx/cells_xtra.v
        read_verilog -lib +/xilinx/brams_bb.v
        read_verilog -lib +/xilinx/drams_bb.v
        hierarchy -check -top <top>

    flatten:     (only if -flatten)
        proc
        flatten

    coarse:
        synth -run coarse

    bram:
        memory_bram -rules +/xilinx/brams.txt
        techmap -map +/xilinx/brams_map.v

    dram:
        memory_bram -rules +/xilinx/drams.txt
        techmap -map +/xilinx/drams_map.v

    fine:
        opt -fast -full
        memory_map
        dffsr2dff
        dff2dffe
        opt -full
        techmap -map +/techmap.v -map +/xilinx/arith_map.v
        opt -fast

    map_luts:
        abc -luts 2:2,3,6:5,10,20 [-dff]
        clean

    map_cells:
        techmap -map +/xilinx/cells_map.v
        dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT
        clean

    check:
        hierarchy -check
        stat
        check -noinit

    edif:     (only if -edif)
        write_edif <file-name>