verific - load Verilog and VHDL designs using Verific

    verific {-vlog95|-vlog2k|-sv2005|-sv2009|-sv} <verilog-file>..

Load the specified Verilog/SystemVerilog files into Verific.


    verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008} <vhdl-file>..

Load the specified VHDL files into Verific.


    verific -import [-gates] {-all | <top-module>..}

Elaborate the design for the specified top modules, import to Yosys and
reset the internal state of Verific. A gate-level netlist is created
when called with -gates.

Visit http://verific.com/ for more information on Verific.