vhdl2verilog - importing VHDL designs using vhdl2verilog

    vhdl2verilog [options] <vhdl-file>..

This command reads VHDL source files using the 'vhdl2verilog' tool and the
Yosys Verilog frontend.

    -out <out_file>
        do not import the vhdl2verilog output. instead write it to the
        specified file.

    -vhdl2verilog_dir <directory>
        do use the specified vhdl2verilog installation. this is the directory
        that contains the setup_env.sh file. when this option is not present,
        it is assumed that vhdl2verilog is in the PATH environment variable.

    -top <top-entity-name>
        The name of the top entity. This option is mandatory.

The following options are passed as-is to vhdl2verilog:

    -arch <architecture_name>
    -unroll_generate
    -nogenericeval
    -nouniquify
    -oldparser
    -suppress <list>
    -quiet
    -nobanner
    -mapfile <file>

vhdl2verilog can be obtained from:
http://www.edautils.com/vhdl2verilog.html