Documentation

This page has links to all the documentaton resources available for Yosys.

Yosys Manual

A quick first-steps tutorial can be found in the README file.

The Yosys manual can be downloaded here (PDF).

Support

The best places to ask questions are the Yosys Subreddit, Stack Overflow and #yosys on freenode. The best place to report a bug is on GitHub.

Presentation Slides

This presentation slides cover a wide range of topics related to Yosys. (The LaTeX source is part of the Yosys source distribution. Fell free to adapt the slides as needed.)

Application Notes

• Yosys AppNote 010: Converting Verilog to BLIF
• Yosys AppNote 011: Interactive Design Investigation
• Yosys AppNote 012: Converting Verilog to BTOR

Papers and other Publications

This section is under construction.

• Clifford Wolf, Johann Glaser. Yosys - A Free Verilog Synthesis Suite. In Proceedings of Austrochip 2013. [download pdf]
• Johann Glaser and Clifford Wolf. Methodology and Example-Driven Interconnect Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable Architectures. In Jan Haase, editor, Models, Methods, and Tools for Complex Chip Design. Lecture Notes in Electrical Engineering. Volume 265, 2014, pp 201-221. Springer, 2013. [download pdf]

In papers and reports, please refer to Yosys as follows: Clifford Wolf. Yosys Open SYnthesis Suite. http://www.clifford.at/yosys/, e.g. using the following BibTeX code:

@MISC{Yosys,
	author = {Clifford Wolf},
	title = {Yosys Open SYnthesis Suite},
	howpublished = "\url{http://www.clifford.at/yosys/}"
}

Command Reference

• abc use ABC for technology mapping
• add add objects to the design
• aigmap map logic to and-inverter-graph circuit
• alumacc extract ALU and MACC cells
• assertpmux convert internal signals to module ports
• attrmap renaming attributes
• attrmvcp move or copy attributes from wires to driving cells
• cd a shortcut for 'select -module <name>'
• check check for obvious problems in the design
• chparam re-evaluate modules with new parameters
• clean remove unused cells and wires
• clk2fflogic convert clocked FFs to generic $ff cells
• connect create or remove connections
• connwrappers replace undef values with defined constants
• copy copy modules in the design
• cover print code coverage counters
• delete delete objects in the design
• deminout demote inout ports to input or output
• design save, restore and reset current design
• dff2dffe transform $dff cells to $dffe cells
• dffinit set INIT param on FF cells
• dfflibmap technology mapping of flip-flops
• dffsr2dff convert DFFSR cells to simpler FF cell types
• dump print parts of the design in ilang format
• echo turning echoing back of commands on and off
• edgetypes list all types of edges in selection
• equiv_add add a $equiv cell
• equiv_induct proving $equiv cells using temporal induction
• equiv_make prepare a circuit for equivalence checking
• equiv_mark mark equivalence checking regions
• equiv_miter extract miter from equiv circuit
• equiv_purge purge equivalence checking module
• equiv_remove remove $equiv cells
• equiv_simple try proving simple $equiv instances
• equiv_status print status of equivalent checking module
• equiv_struct structural equivalence checking
• eval evaluate the circuit given an input
• expose convert internal signals to module ports
• extract find subcircuits and replace them with cells
• flatten flatten design
• freduce perform functional reduction
• fsm extract and optimize finite state machines
• fsm_detect finding FSMs in design
• fsm_expand expand FSM cells by merging logic into it
• fsm_export exporting FSMs to KISS2 files
• fsm_extract extracting FSMs in design
• fsm_info print information on finite state machines
• fsm_map mapping FSMs to basic logic
• fsm_opt optimize finite state machines
• fsm_recode recoding finite state machines
• greenpak4_counters Extract GreenPak4 counter cells
• greenpak4_dffinv merge greenpak4 inverters and DFFs
• help display help messages
• hierarchy check, expand and clean up design hierarchy
• hilomap technology mapping of constant hi- and/or lo-drivers
• history show last interactive commands
• ice40_ffinit iCE40: handle FF init values
• ice40_ffssr iCE40: merge synchronous set/reset into FF cells
• ice40_opt iCE40: perform simple optimizations
• insbuf insert buffer cells for connected wires
• iopadmap technology mapping of i/o pads (or buffers)
• json write design in JSON format
• log print text and log files
• ls list modules or objects in modules
• lut2mux convert $lut to $_MUX_
• maccmap mapping macc cells
• memory translate memories to basic cells
• memory_bram map memories to block rams
• memory_collect creating multi-port memory cells
• memory_dff merge input/output DFFs into memories
• memory_map translate multiport memories to basic cells
• memory_memx emulate vlog sim behavior for mem ports
• memory_share consolidate memory ports
• memory_unpack unpack multi-port memory cells
• miter automatically create a miter circuit
• muxcover cover trees of MUX cells with wider MUXes
• nlutmap map to LUTs of different sizes
• opt perform simple optimizations
• opt_clean remove unused cells and wires
• opt_expr perform const folding and simple expression rewriting
• opt_merge consolidate identical cells
• opt_muxtree eliminate dead trees in multiplexer trees
• opt_reduce simplify large MUXes and AND/OR gates
• opt_rmdff remove DFFs with constant inputs
• plugin load and list loaded plugins
• pmuxtree transform $pmux cells to trees of $mux cells
• prep generic synthesis script
• proc translate processes to netlists
• proc_arst detect asynchronous resets
• proc_clean remove empty parts of processes
• proc_dff extract flip-flops from processes
• proc_dlatch extract latches from processes
• proc_init convert initial block to init attributes
• proc_mux convert decision trees to multiplexers
• proc_rmdead eliminate dead trees in decision trees
• qwp quadratic wirelength placer
• read_blif read BLIF file
• read_ilang read modules from ilang file
• read_liberty read cells from liberty file
• read_verilog read modules from Verilog file
• rename rename object in the design
• sat solve a SAT problem in the circuit
• scatter add additional intermediate nets
• scc detect strongly connected components (logic loops)
• script execute commands from script file
• select modify and view the list of selected objects
• setattr set/unset attributes on objects
• setparam set/unset parameters on objects
• setundef replace undef values with defined constants
• share perform sat-based resource sharing
• shell enter interactive command mode
• show generate schematics using graphviz
• shregmap map shift registers
• simplemap mapping simple coarse-grain cells
• singleton create singleton modules
• splice create explicit splicing cells
• splitnets split up multi-bit nets
• stat print some statistics
• submod moving part of a module to a new submodule
• synth generic synthesis script
• synth_gowin synthesis for Gowin FPGAs
• synth_greenpak4 synthesis for GreenPAK4 FPGAs
• synth_ice40 synthesis for iCE40 FPGAs
• synth_xilinx synthesis for Xilinx FPGAs
• tcl execute a TCL script file
• techmap generic technology mapper
• tee redirect command output to file
• test_abcloop automatically test handling of loops in abc command
• test_autotb generate simple test benches
• test_cell automatically test the implementation of a cell type
• torder print cells in topological order
• trace redirect command output to file
• tribuf infer tri-state buffers
• verific load Verilog and VHDL designs using Verific
• verilog_defaults set default options for read_verilog
• vhdl2verilog importing VHDL designs using vhdl2verilog
• wreduce reduce the word size of operations if possible
• write_blif write design to BLIF file
• write_btor write design to BTOR file
• write_edif write design to EDIF netlist file
• write_file write a text to a file
• write_ilang write design to ilang file
• write_intersynth write design to InterSynth netlist file
• write_json write design to a JSON file
• write_smt2 write design to SMT-LIBv2 file
• write_smv write design to SMV file
• write_spice write design to SPICE netlist file
• write_verilog write design to Verilog file
• zinit add inverters so all FF are zero-initialized